yosys/tests/opt/bug4610.ys

read_rtlil <<EOT
autoidx 1
module \top
  wire output 1 \Y
  cell $reduce_or $reduce_or$rtl.v:29$20
    parameter \A_SIGNED 0
    parameter \A_WIDTH 0
    parameter \Y_WIDTH 1
    connect \A { }
    connect \Y \Y
  end
end
EOT

equiv_opt -assert opt_demorgan
tests: replace read_ilang with read_rtlil * #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil 2024-11-20 07:54:23 -06:00			`read_rtlil <<EOT`
opt_demorgan: add test for zero width cell 2024-09-25 10:10:16 -05:00			`autoidx 1`
			`module \top`
			`wire output 1 \Y`
			`cell $reduce_or $reduce_or$rtl.v:29$20`
			`parameter \A_SIGNED 0`
			`parameter \A_WIDTH 0`
			`parameter \Y_WIDTH 1`
			`connect \A { }`
			`connect \Y \Y`
			`end`
			`end`
			`EOT`

			`equiv_opt -assert opt_demorgan`