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26 lines
785 B
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26 lines
785 B
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.. _sec:celllib_gates:
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Gate-level cells
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----------------
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For gate level logic networks, fixed function single bit cells are used that do
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not provide any parameters.
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Simulation models for these cells can be found in the file
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:file:`techlibs/common/simcells.v` in the Yosys source tree.
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In most cases gate level logic networks are created from RTL networks using the
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techmap pass. The flip-flop cells from the gate level logic network can be
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mapped to physical flip-flop cells from a Liberty file using the dfflibmap pass.
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The combinatorial logic cells can be mapped to physical cells from a Liberty
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file via ABC using the abc pass.
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.. toctree::
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:maxdepth: 2
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/cell/gate_comb_simple
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/cell/gate_comb_combined
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/cell/gate_reg_ff
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/cell/gate_reg_latch
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/cell/gate_other
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