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yosys/tests/verilog/unbased_unsized_tern.sv

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verilog: use derived module info to elaborate cell connections - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
2021-10-19 19:46:26 -05:00
module pass_through #(
parameter WIDTH = 1
) (
input logic [WIDTH-1:0] inp,
output logic [WIDTH-1:0] out
);
assign out = inp;
endmodule
module gate (
input logic inp,
output logic [63:0]
out1, out2, out3, out4
);
pass_through #(40) pt1('1, out1);
pass_through #(40) pt2(inp ? '1 : '0, out2);
pass_through #(40) pt3(inp ? '1 : 2'b10, out3);
pass_through #(40) pt4(inp ? '1 : inp, out4);
endmodule
module gold (
input logic inp,
output logic [63:0]
out1, out2, out3, out4
);
localparam ONES = 40'hFF_FFFF_FFFF;
pass_through #(40) pt1(ONES, out1);
pass_through #(40) pt2(inp ? ONES : 0, out2);
pass_through #(40) pt3(inp ? ONES : 2'sb10, out3);
pass_through #(40) pt4(inp ? ONES : inp, out4);
endmodule