yosys/tests/lut/check_map.ys

simplemap
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
design -load postopt
equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
design -load postopt
select -assert-count 0 t:* t:$lut %d
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-04 22:50:38 -06:00			`simplemap`
cmp2lut: new techmap pass. 2019-01-02 01:53:31 -06:00			`equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v`
equiv_opt: new command, for verifying optimization passes. 2018-12-06 08:28:20 -06:00			`design -load postopt`
cmp2lut: new techmap pass. 2019-01-02 01:53:31 -06:00			`equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v`
			`design -load postopt`
			`select -assert-count 0 t:* t:$lut %d`