mirror of https://github.com/YosysHQ/yosys.git
46 lines
962 B
Plaintext
46 lines
962 B
Plaintext
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read_verilog -sv <<EOT
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module peepopt_formal_clockgateff_0(
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input logic clk_i,
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input logic ena_i,
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input logic enb_i,
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output logic clk_o
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);
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logic en_latched;
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always_latch
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if (!clk_i)
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en_latched <= ena_i | enb_i;
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assign clk_o = en_latched & clk_i;
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endmodule
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EOT
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# Check original design has latch
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prep -auto-top
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select -assert-count 1 t:$dlatch
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select -assert-count 0 t:$dff
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# Manually execute equiv_opt like pattern so clk2fflogic is called with
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# -nopeepopt, otherwise this doesn't test anything
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design -save preopt
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check -assert
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peepopt -formalclk
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check -assert
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design -stash postopt
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# Create miter and clk2fflogic without peepopt
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design -copy-from preopt -as gold A:top
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design -copy-from postopt -as gate A:top
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clk2fflogic -nopeepopt
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equiv_make gold gate equiv
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equiv_induct equiv
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equiv_status -assert equiv
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# Check final design has dff instead of latch
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design -load postopt
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clean
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select -assert-count 0 t:$dlatch
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select -assert-count 1 t:$dff
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