mirror of https://github.com/YosysHQ/yosys.git
104 lines
3.1 KiB
C++
104 lines
3.1 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void assertpmux_worker(Cell *pmux, bool flag_noinit)
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{
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Module *module = pmux->module;
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log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
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int swidth = pmux->getParam("\\S_WIDTH").as_int();
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int cntbits = ceil_log2(swidth+1);
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SigSpec sel = pmux->getPort("\\S");
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SigSpec cnt(State::S0, cntbits);
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for (int i = 0; i < swidth; i++)
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cnt = module->Add(NEW_ID, cnt, sel[i]);
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SigSpec assert_a = module->Le(NEW_ID, cnt, SigSpec(1, cntbits));
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SigSpec assert_en = State::S1;
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if (flag_noinit) {
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Cell *initstate_cell = module->addCell(NEW_ID, "$initstate");
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SigSpec initstate_sig = module->addWire(NEW_ID);
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initstate_cell->setPort("\\Y", initstate_sig);
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assert_en = module->LogicNot(NEW_ID, initstate_sig);
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}
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Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en);
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if (pmux->attributes.count("\\src") != 0)
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assert_cell->attributes["\\src"] = pmux->attributes.at("\\src");
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}
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struct AssertpmuxPass : public Pass {
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AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" assertpmux [options] [selection]\n");
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log("\n");
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log("This command adds asserts to the design that assert that all parallel muxes\n");
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log("($pmux cells) have a maximum of one of their inputs enable at any time.\n");
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log("\n");
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log(" -noinit\n");
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log(" do not enforce the pmux condition during the init state\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_noinit = false;
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log_header(design, "Executing ASSERTPMUX pass (add asserts for $pmux cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-noinit") {
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flag_noinit = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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vector<Cell*> pmux_cells;
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for (auto cell : module->selected_cells())
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if (cell->type == "$pmux")
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pmux_cells.push_back(cell);
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for (auto cell : pmux_cells)
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assertpmux_worker(cell, flag_noinit);
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}
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}
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} AssertpmuxPass;
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PRIVATE_NAMESPACE_END
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