2019-09-10 00:08:03 -05:00
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read_verilog div_mod.v
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hierarchy -top top
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flatten
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 12 t:LUT1
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2019-09-11 12:34:22 -05:00
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select -assert-count 23 t:LUT2
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2019-09-11 13:28:40 -05:00
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select -assert-count 12 t:LUT4
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2019-09-11 22:24:18 -05:00
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select -assert-count 9 t:LUT5
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2019-09-11 23:13:49 -05:00
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select -assert-count 84 t:LUT6
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2019-09-10 00:08:03 -05:00
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select -assert-count 65 t:MUXCY
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select -assert-count 36 t:MUXF7
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select -assert-count 9 t:MUXF8
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select -assert-count 28 t:XORCY
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select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
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