mirror of https://github.com/YosysHQ/yosys.git
14 lines
256 B
Verilog
14 lines
256 B
Verilog
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module demo9;
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(* maximize *) wire[7:0] h = $anyconst;
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wire [7:0] i = $allconst;
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wire [7:0] t0 = ((i << 8'b00000010) + 8'b00000011);
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wire trigger = (t0 > h) && (h < 8'b00000100);
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always @* begin
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assume(trigger == 1'b1);
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cover(1);
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end
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endmodule
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