mirror of https://github.com/YosysHQ/yosys.git
23 lines
589 B
Plaintext
23 lines
589 B
Plaintext
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# Our implementation
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read_verilog ../arith_map.v
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read_verilog ../cells_sim.v
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read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
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rename \$__SF2_ALU gate
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hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
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flatten
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opt
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write_verilog gate.v
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# The reference
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read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
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rename \$alu gold
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hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
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flatten
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proc
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clean
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write_verilog gold.v
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read_verilog gate.v
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miter -equiv -flatten -make_outputs gold gate miter
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sat -verify -prove trigger 0 -show-ports miter
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