mirror of https://github.com/YosysHQ/yosys.git
24 lines
424 B
Verilog
24 lines
424 B
Verilog
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module $__DPR16X4C_ (...);
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parameter INIT = 64'b0;
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input PORT_W_CLK;
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input [3:0] PORT_W_ADDR;
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input [3:0] PORT_W_WR_DATA;
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input PORT_W_WR_EN;
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input [3:0] PORT_R_ADDR;
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output [3:0] PORT_R_RD_DATA;
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DPR16X4C #(
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.INITVAL($sformatf("0x%08x", INIT))
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) _TECHMAP_REPLACE_ (
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.RAD(PORT_R_ADDR),
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.DO(PORT_R_RD_DATA),
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.WAD(PORT_W_ADDR),
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.DI(PORT_W_WR_DATA),
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.WCK(PORT_W_CLK),
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.WRE(PORT_W_WR_EN)
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);
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endmodule
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