mirror of https://github.com/YosysHQ/yosys.git
14 lines
286 B
Plaintext
14 lines
286 B
Plaintext
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read_verilog <<EOT
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module top(input e, d, output q);
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reg l;
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always @*
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if (e)
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l = ~d;
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assign q = ~l;
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endmodule
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EOT
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_ecp5 -abc9
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select -assert-count 2 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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