mirror of https://github.com/YosysHQ/yosys.git
30 lines
856 B
Plaintext
30 lines
856 B
Plaintext
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read_verilog ../../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
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design -load postopt
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cd latchp
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select -assert-count 1 t:latchsre
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select -assert-none t:latchsre %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
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design -load postopt
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cd latchn
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select -assert-count 1 t:latchnsre
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select -assert-none t:latchnsre %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
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design -load postopt
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cd latchsr
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select -assert-count 2 t:$lut
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select -assert-count 1 t:latchnsre
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select -assert-none t:$lut t:latchnsre %% t:* %D
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