mirror of https://github.com/YosysHQ/yosys.git
22 lines
1.0 KiB
Plaintext
22 lines
1.0 KiB
Plaintext
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read_verilog ../../common/dffs.v
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rename dff my_dff # Work around conflicting module names between test and vendor cells
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rename dffe my_dffe
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design -save read
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hierarchy -top my_dff
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:sdffsre
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select -assert-none t:sdffsre %% t:* %D
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design -load read
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hierarchy -top my_dffe
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proc
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equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:sdffsre
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select -assert-none t:sdffsre %% t:* %D
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