mirror of https://github.com/YosysHQ/yosys.git
39 lines
820 B
Plaintext
39 lines
820 B
Plaintext
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read_verilog <<EOT
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module top(input in, output out);
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wire [1:0] w1, w2;
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f1_test u1 (.in(in), .out(w1[0]));
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f2_test u2 (.in(w1), .out(w2));
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f3_test u3 (.in(w2[0]), .out(out));
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endmodule
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module f1_test(input in, output out);
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assign out = in;
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endmodule
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module f2_test(input [1:0] in, output [1:0] out);
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assign out[0] = in[0];
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assign out[1] = in[1];
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endmodule
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module f3_test(input in, output [1:0] out);
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assign out[0] = in;
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assign out[1] = in;
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endmodule
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EOT
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hierarchy -top top
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flatten -scopename
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prep
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write_json json_scopeinfo.out
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!grep -qvF '$scopeinfo' json_scopeinfo.out
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write_json -scopeinfo json_scopeinfo.out
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!grep -qF '$scopeinfo' json_scopeinfo.out
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json -o json_scopeinfo.out
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!grep -qvF '$scopeinfo' json_scopeinfo.out
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json -scopeinfo -o json_scopeinfo.out
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!grep -qF '$scopeinfo' json_scopeinfo.out
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