2013-10-26 10:22:29 -05:00
|
|
|
#!/bin/bash
|
|
|
|
|
|
|
|
set -ex
|
|
|
|
|
2013-10-27 03:52:00 -05:00
|
|
|
XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
|
2013-10-26 10:22:29 -05:00
|
|
|
XILINX_PART=xc6slx9-2-tqg144
|
|
|
|
|
2013-10-27 03:52:00 -05:00
|
|
|
../../../yosys - <<- EOT
|
|
|
|
read_verilog example.v
|
|
|
|
synth_xilinx -edif synth.edif
|
2013-10-26 10:22:29 -05:00
|
|
|
EOT
|
|
|
|
|
|
|
|
$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
|
|
|
|
$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
|
|
|
|
$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
|
|
|
|
$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
|
2013-10-27 03:52:00 -05:00
|
|
|
$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf
|
2013-10-26 10:22:29 -05:00
|
|
|
|