yosys/techlibs/xilinx/brams.txt

21 lines
305 B
Plaintext
Raw Normal View History

2014-12-31 09:53:53 -06:00
# This is a very simplified description of the capabilities of
# the Xilinx RAMB36 core. But it is a start..
#
bram XILINX_RAMB36_SDP32
init 1
abits 10
dbits 32
groups 2
2014-12-31 15:50:08 -06:00
ports 1 1
wrmode 1 0
enable 4 0
2014-12-31 09:53:53 -06:00
transp 0 2
clocks 1 2
endbram
match XILINX_RAMB36_SDP32
min bits 1024
endmatch