mirror of https://github.com/YosysHQ/yosys.git
258 lines
12 KiB
Python
258 lines
12 KiB
Python
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#!/usr/bin/env python3
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from argparse import ArgumentParser
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from io import StringIO
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from enum import Enum, auto
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import os.path
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import sys
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class Cell:
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def __init__(self, name, keep=False, port_attrs={}):
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self.name = name
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self.keep = keep
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self.port_attrs = port_attrs
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CELLS = [
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# Design elements types listed in Xilinx UG953
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Cell('BSCANE2', keep=True),
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# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
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#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
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Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
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Cell('CAPTUREE2', keep=True),
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# Cell('CARRY4'),
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Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('DCIRESET', keep=True),
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Cell('DNA_PORT'),
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Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('EFUSE_USR'),
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# Cell('FDCE'),
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# Cell('FDPE'),
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# Cell('FDRE'),
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# Cell('FDSE'),
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Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('FRAME_ECCE2'),
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Cell('GTHE2_CHANNEL'),
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Cell('GTHE2_COMMON'),
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Cell('GTPE2_CHANNEL'),
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Cell('GTPE2_COMMON'),
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Cell('GTXE2_CHANNEL'),
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Cell('GTXE2_COMMON'),
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# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
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Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
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Cell('ICAPE2', keep=True),
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Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
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Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
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Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
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Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
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Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
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Cell('ISERDESE2', port_attrs={
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'CLK': ['clkbuf_sink'],
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'CLKB': ['clkbuf_sink'],
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'OCLK': ['clkbuf_sink'],
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'OCLKB': ['clkbuf_sink'],
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'CLKDIV': ['clkbuf_sink'],
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'CLKDIVP': ['clkbuf_sink'],
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}),
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Cell('KEEPER'),
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Cell('LDCE'),
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Cell('LDPE'),
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# Cell('LUT1'),
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# Cell('LUT2'),
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# Cell('LUT3'),
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# Cell('LUT4'),
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# Cell('LUT5'),
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# Cell('LUT6'),
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#Cell('LUT6_2'),
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Cell('MMCME2_ADV'),
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Cell('MMCME2_BASE'),
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# Cell('MUXF7'),
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# Cell('MUXF8'),
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# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
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Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
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Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
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Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
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Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
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Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
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Cell('PHASER_IN'),
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Cell('PHASER_IN_PHY'),
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Cell('PHASER_OUT'),
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Cell('PHASER_OUT_PHY'),
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Cell('PHASER_REF'),
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Cell('PHY_CONTROL'),
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Cell('PLLE2_ADV'),
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Cell('PLLE2_BASE'),
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Cell('PS7', keep=True),
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Cell('PULLDOWN'),
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Cell('PULLUP'),
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#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
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#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
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Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
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# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
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Cell('ROM128X1'),
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Cell('ROM256X1'),
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Cell('ROM32X1'),
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Cell('ROM64X1'),
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#Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
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#Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
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Cell('STARTUPE2', keep=True),
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Cell('USR_ACCESSE2'),
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Cell('XADC'),
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]
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class State(Enum):
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OUTSIDE = auto()
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IN_MODULE = auto()
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IN_OTHER_MODULE = auto()
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IN_FUNCTION = auto()
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IN_TASK = auto()
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def xtract_cell_decl(cell, dirs, outf):
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for dir in dirs:
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fname = os.path.join(dir, cell.name + '.v')
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try:
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with open(fname) as f:
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state = State.OUTSIDE
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found = False
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# Probably the most horrible Verilog "parser" ever written.
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for l in f:
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l = l.partition('//')[0]
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l = l.strip()
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if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
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if found:
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print('Multiple modules in {}.'.format(fname))
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sys.exit(1)
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elif state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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found = True
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state = State.IN_MODULE
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if cell.keep:
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outf.write('(* keep *)\n')
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outf.write('module {} (...);\n'.format(cell.name))
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elif l.startswith('module '):
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if state != State.OUTSIDE:
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print('Nested modules in {}.'.format(fname))
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sys.exit(1)
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state = State.IN_OTHER_MODULE
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elif l.startswith('task '):
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if state == State.IN_MODULE:
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state = State.IN_TASK
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elif l.startswith('function '):
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if state == State.IN_MODULE:
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state = State.IN_FUNCTION
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elif l == 'endtask':
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if state == State.IN_TASK:
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state = State.IN_MODULE
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elif l == 'endfunction':
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if state == State.IN_FUNCTION:
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state = State.IN_MODULE
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elif l == 'endmodule':
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if state == State.IN_MODULE:
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outf.write(l + '\n')
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outf.write('\n')
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elif state != State.IN_OTHER_MODULE:
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print('endmodule in weird place in {}.'.format(cell.name, fname))
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sys.exit(1)
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state = State.OUTSIDE
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elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
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if l.endswith((';', ',')):
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l = l[:-1]
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if ';' in l:
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print('Weird port line in {} [{}].'.format(fname, l))
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sys.exit(1)
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kind, _, ports = l.partition(' ')
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for port in ports.split(','):
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port = port.strip()
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for attr in cell.port_attrs.get(port, []):
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outf.write(' (* {} *)\n'.format(attr))
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outf.write(' {} {};\n'.format(kind, port))
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elif l.startswith('parameter ') and state == State.IN_MODULE:
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if 'UNPLACED' in l:
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continue
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if l.endswith((';', ',')):
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l = l[:-1]
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while ' ' in l:
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l = l.replace(' ', ' ')
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if ';' in l:
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print('Weird parameter line in {} [{}].'.format(fname, l))
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sys.exit(1)
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outf.write(' {};\n'.format(l))
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if state != State.OUTSIDE:
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print('endmodule not found in {}.'.format(fname))
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sys.exit(1)
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if not found:
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print('Cannot find module {} in {}.'.format(cell.name, fname))
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sys.exit(1)
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return
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except FileNotFoundError:
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continue
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print('Cannot find {}.'.format(cell.name))
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sys.exit(1)
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if __name__ == '__main__':
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parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from Vivado.')
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parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
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args = parser.parse_args()
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dirs = [
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os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
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os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
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]
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for dir in dirs:
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if not os.path.isdir(dir):
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print('{} is not a directory'.format(dir))
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out = StringIO()
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for cell in CELLS:
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xtract_cell_decl(cell, dirs, out)
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with open('cells_xtra.v', 'w') as f:
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f.write('// Created by cells_xtra.py from Xilinx models\n')
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f.write('\n')
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f.write(out.getvalue())
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