mirror of https://github.com/YosysHQ/yosys.git
16 lines
303 B
Verilog
16 lines
303 B
Verilog
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module top(out);
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genvar i;
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generate
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for (i = 0; i < 2; i = i + 1) begin : loop
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localparam j = i + 1;
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if (1) begin : blk
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localparam i = j + 1;
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wire [i:0] x;
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assign x = 1'sb1;
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end
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end
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endgenerate
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output wire [63:0] out;
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assign out = {loop[0].blk.x, loop[1].blk.x};
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endmodule
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