mirror of https://github.com/YosysHQ/yosys.git
22 lines
242 B
Verilog
22 lines
242 B
Verilog
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module top(o1, o2, o3);
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output wire o1;
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`define COND_1
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`define COND_2
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`define COND_3
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`ifdef COND_1
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output wire o2;
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`elsif COND_2
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input wire dne1;
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`elsif COND_3
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input wire dne2;
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`else
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input wire dne3;
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`endif
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output wire o3;
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endmodule
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