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50 lines
1.2 KiB
Verilog
50 lines
1.2 KiB
Verilog
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// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
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// the constant and non-constant case evaluation logic is covered
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module top(
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// expected to output all 1s
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output reg a, b, c, d, e, f, g, h
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);
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initial begin
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case (2'b0)
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1'b0: a = 1;
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default: a = 0;
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endcase
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case (2'sb11)
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2'sb01: b = 0;
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1'sb1: b = 1;
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endcase
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case (2'sb11)
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1'sb0: c = 0;
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1'sb1: c = 1;
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endcase
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case (2'sb11)
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1'b0: d = 0;
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1'sb1: d = 0;
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default: d = 1;
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endcase
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case (2'b11)
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1'sb0: e = 0;
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1'sb1: e = 0;
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default: e = 1;
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endcase
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case (1'sb1)
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1'sb0: f = 0;
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2'sb11: f = 1;
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default: f = 0;
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endcase
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case (1'sb1)
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1'sb0: g = 0;
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3'b0: g = 0;
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2'sb11: g = 0;
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default: g = 1;
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endcase
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case (1'sb1)
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1'sb0: h = 0;
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1'b1: h = 1;
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3'b0: h = 0;
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2'sb11: h = 0;
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default: h = 0;
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endcase
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end
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endmodule
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