2021-03-16 21:34:30 -05:00
|
|
|
read_verilog ../common/mux.v
|
|
|
|
design -save read
|
|
|
|
|
|
|
|
hierarchy -top mux2
|
|
|
|
proc
|
|
|
|
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
cd mux2 # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 1 t:LUT3
|
|
|
|
select -assert-count 3 t:inpad
|
|
|
|
select -assert-count 1 t:outpad
|
|
|
|
|
|
|
|
select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
|
|
|
|
|
|
|
|
design -load read
|
|
|
|
hierarchy -top mux4
|
|
|
|
proc
|
|
|
|
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
cd mux4 # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 3 t:LUT3
|
|
|
|
select -assert-count 6 t:inpad
|
|
|
|
select -assert-count 1 t:outpad
|
|
|
|
|
|
|
|
select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
|
|
|
|
|
|
|
|
design -load read
|
|
|
|
hierarchy -top mux8
|
|
|
|
proc
|
|
|
|
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
cd mux8 # Constrain all select calls below inside the top module
|
2021-04-12 04:33:40 -05:00
|
|
|
select -assert-count 1 t:LUT1
|
2021-03-16 21:34:30 -05:00
|
|
|
select -assert-count 1 t:LUT3
|
|
|
|
select -assert-count 2 t:mux4x0
|
|
|
|
select -assert-count 11 t:inpad
|
|
|
|
select -assert-count 1 t:outpad
|
|
|
|
|
2021-04-12 04:33:40 -05:00
|
|
|
select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
|
2021-03-16 21:34:30 -05:00
|
|
|
|
|
|
|
design -load read
|
|
|
|
hierarchy -top mux16
|
|
|
|
proc
|
|
|
|
equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
|
|
cd mux16 # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 1 t:LUT3
|
|
|
|
select -assert-count 2 t:mux8x0
|
|
|
|
select -assert-count 20 t:inpad
|
|
|
|
select -assert-count 1 t:outpad
|
|
|
|
|
|
|
|
select -assert-none t:LUT3 t:mux8x0 t:inpad t:outpad %% t:* %D
|