mirror of https://github.com/YosysHQ/yosys.git
13 lines
197 B
Verilog
13 lines
197 B
Verilog
|
module top;
|
||
|
|
mid mid_uut ();
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module mid ();
|
||
|
|
bot bot_uut ();
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module bot ();
|
||
|
|
initial $display("%%l: %l\n%%m: %m");
|
||
|
|
always $display("%%l: %l\n%%m: %m");
|
||
|
|
endmodule
|