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yosys/docs/source/code_examples/intro/counter.ys

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Fixed trailing whitespaces
2015-07-02 04:14:30 -05:00
# read design
presentation progress
2014-01-29 05:15:38 -06:00
read_verilog counter.v
hierarchy -check -top counter
Add cell_libs.rst Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
2023-12-13 15:08:46 -06:00
show -notitle -format dot -prefix counter_00
presentation progress
2014-01-29 05:15:38 -06:00
# the high-level stuff
Add cell_libs.rst Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
2023-12-13 15:08:46 -06:00
proc; opt
memory; opt
fsm; opt
show -notitle -format dot -prefix counter_01
presentation progress
2014-01-29 05:15:38 -06:00
# mapping to internal cell library
Progress in presentation
2014-06-26 15:05:39 -05:00
techmap; opt
presentation progress
2014-01-29 05:15:38 -06:00
Add cell_libs.rst Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
2023-12-13 15:08:46 -06:00
splitnets -ports;; show -notitle -format dot -prefix counter_02
presentation progress
2014-01-29 05:15:38 -06:00
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
Add cell_libs.rst Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`. `example_synth.rst` still pending updated example.
2023-12-13 15:08:46 -06:00
show -notitle -lib mycells.v -format dot -prefix counter_03
Move presentation intro example Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
2023-08-02 16:20:29 -05:00
# write synthesized design
write_verilog synth.v