mirror of https://github.com/YosysHQ/yosys.git
25 lines
475 B
Verilog
25 lines
475 B
Verilog
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module $__ICE40_SPRAM_ (...);
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input [3:0] PORT_A_WR_BE;
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input [13:0] PORT_A_ADDR;
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input [15:0] PORT_A_WR_DATA;
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output [15:0] PORT_A_RD_DATA;
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SB_SPRAM256KA _TECHMAP_REPLACE_ (
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.ADDRESS(PORT_A_ADDR),
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.DATAIN(PORT_A_WR_DATA),
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.MASKWREN(PORT_A_WR_BE),
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.WREN(PORT_A_WR_EN),
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.CHIPSELECT(PORT_A_CLK_EN),
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.CLOCK(PORT_A_CLK),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(PORT_A_RD_DATA),
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);
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endmodule
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