mirror of https://github.com/YosysHQ/yosys.git
7 lines
149 B
Plaintext
7 lines
149 B
Plaintext
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read_verilog sym_mul_test.v
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hierarchy -check -top test
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techmap -map sym_mul_map.v;;
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show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v
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