mirror of https://github.com/YosysHQ/yosys.git
8 lines
174 B
Plaintext
8 lines
174 B
Plaintext
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read_verilog red_or3x1_test.v
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hierarchy -check -top test
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techmap -map red_or3x1_map.v;;
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splitnets -ports
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show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v
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