mirror of https://github.com/YosysHQ/yosys.git
16 lines
331 B
Plaintext
16 lines
331 B
Plaintext
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read_verilog mymul_test.v
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hierarchy -check -top test
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techmap -map sym_mul_map.v \
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-map mymul_map.v;;
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rename test test_mapped
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read_verilog mymul_test.v
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miter -equiv test test_mapped miter
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flatten miter
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sat -verify -prove trigger 0 miter
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splitnets -ports test_mapped/A
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show -prefix mymul -format dot -notitle test_mapped
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