yosys/tests/verilog/genfor_decl_no_sv.ys

logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1
read_verilog <<EOT
module top;
    for (genvar i = 1; i < 10; i = i + 1)
        wire x;
endmodule
EOT
sv: support declaration in generate for initialization This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected. 2021-08-31 12:45:02 -05:00			`logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1`
			`read_verilog <<EOT`
			`module top;`
			`for (genvar i = 1; i < 10; i = i + 1)`
			`wire x;`
			`endmodule`
			`EOT`