mirror of https://github.com/YosysHQ/yosys.git
22 lines
366 B
Verilog
22 lines
366 B
Verilog
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module top #(
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parameter WIDTH = 6
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) (
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input [WIDTH-1:0] a_i,
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input [WIDTH-1:0] b_i,
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output [WIDTH-1:0] z_o
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);
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genvar g;
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generate
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for (g = 0; g < WIDTH; g = g + 1) begin
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if (g > 2) begin
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wire tmp;
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assign tmp = a_i[g] || b_i[g];
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assign z_o[g] = tmp;
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end
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else begin
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assign z_o[g] = a_i[g] && b_i[g];
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end
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end
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endgenerate
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endmodule
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