mirror of https://github.com/YosysHQ/yosys.git
7 lines
134 B
Verilog
7 lines
134 B
Verilog
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module MYMUL(A, B, Y);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output [WIDTH-1:0] Y;
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assign Y = A * B;
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endmodule
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