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yosys/tests/simple/specify.v

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First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
2018-03-04 15:35:08 -06:00
module test_specify;
specparam a=1;
specify
endspecify
specify
(A => B) = ( 1 ) ;
(A- => B) = ( 1,2 ) ;
(A+ => B) = ( 1,2,3 ) ;
(A => B) = (
1.1, 2, 3,
4, 5.5, 6.6
) ;
(A => B) = (
1.1, 2, 3,
4, 5.5, 6.6 ,
7.7, 8.8, 9,
10.1, 11, 12
) ;
Fix tests/simple/specify.v Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 07:31:19 -05:00
specparam b=1;
First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
2018-03-04 15:35:08 -06:00
specparam [1:2] asasa=1;
endspecify
specify
Fix tests/simple/specify.v Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 07:31:19 -05:00
specparam c=1:2:3;
First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
2018-03-04 15:35:08 -06:00
endspecify
endmodule