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24 lines
476 B
Systemverilog
24 lines
476 B
Systemverilog
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module gate(w, x, y, z);
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function automatic integer bar(
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integer a
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);
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bar = 2 ** a;
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endfunction
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output integer w = bar(4);
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function automatic integer foo(
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input integer a, /* implicitly input */ integer b,
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output integer c, /* implicitly output */ integer d
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);
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c = 42;
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d = 51;
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foo = a + b + 1;
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endfunction
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output integer x, y, z;
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initial x = foo(1, 2, y, z);
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endmodule
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module gold(w, x, y, z);
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output integer w = 16, x = 4, y = 42, z = 51;
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endmodule
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