mirror of https://github.com/YosysHQ/yosys.git
11 lines
250 B
Plaintext
11 lines
250 B
Plaintext
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read_verilog counters.v
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proc; opt
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expose -shared counter1 counter2
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miter -equiv -make_assert -make_outputs counter1 counter2 miter
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cd miter; flatten; opt
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sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs
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