mirror of https://github.com/YosysHQ/yosys.git
55 lines
1.9 KiB
C++
55 lines
1.9 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct CopyPass : public Pass {
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CopyPass() : Pass("copy", "copy modules in the design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" copy old_name new_name\n");
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log("\n");
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log("Copy the specified module. Note that selection patterns are not supported\n");
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log("by this command.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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if (args.size() != 3)
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log_cmd_error("Invalid number of arguments!\n");
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std::string src_name = RTLIL::escape_id(args[1]);
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std::string trg_name = RTLIL::escape_id(args[2]);
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if (design->modules.count(src_name) == 0)
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log_cmd_error("Can't find source module %s.\n", src_name.c_str());
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if (design->modules.count(trg_name) != 0)
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log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
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design->modules[trg_name] = design->modules.at(src_name)->clone();
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design->modules[trg_name]->name = trg_name;
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}
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} CopyPass;
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