yosys/tests/asicworld/code_verilog_tutorial_simpl...

11 lines
132 B
Coq
Raw Normal View History

2013-01-05 04:13:26 -06:00
module simple_function();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
endmodule