mirror of https://github.com/YosysHQ/yosys.git
42 lines
1.4 KiB
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42 lines
1.4 KiB
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.. _chapter:overview:
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Yosys internals
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===============
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.. TODO: copypaste
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Yosys is an extensible open source hardware synthesis tool. It is aimed at
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designers who are looking for an easily accessible, universal, and
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vendor-independent synthesis tool, as well as scientists who do research in
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electronic design automation (EDA) and are looking for an open synthesis
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framework that can be used to test algorithms on complex real-world designs.
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Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
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wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
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`openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
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.. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
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.. _openMSP430 CPU: http://opencores.org/projects/openmsp430
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.. _OpenCores I2C master: http://opencores.org/projects/i2c
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.. _k68 CPU: http://opencores.org/projects/k68
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As of this writing a Yosys VHDL frontend is in development.
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Yosys is written in C++ (using some features from the new C++11 standard). This
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chapter describes some of the fundamental Yosys data structures. For the sake of
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simplicity the C++ type names used in the Yosys implementation are used in this
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chapter, even though the chapter only explains the conceptual idea behind it and
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can be used as reference to implement a similar system in any language.
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.. toctree::
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flow/index
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formats/index
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techmap
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extensions
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.. TODO: copypaste
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