mirror of https://github.com/YosysHQ/yosys.git
13 lines
177 B
Verilog
13 lines
177 B
Verilog
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module sumprod(a, b, c, sum, prod);
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input [7:0] a, b, c;
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output [7:0] sum, prod;
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{* sumstuff *}
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assign sum = a + b + c;
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{* *}
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assign prod = a * b * c;
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endmodule
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