yosys/tests/rpc/design.v

module top(input [3:0] i, output [3:0] o);
	python_inv #(
	  .width(4)
	) inv (
		.i(i),
		.o(o),
	);
endmodule
rpc: new frontend. A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design. 2019-09-25 22:57:16 -05:00			`module top(input [3:0] i, output [3:0] o);`
			`python_inv #(`
			`.width(4)`
			`) inv (`
			`.i(i),`
			`.o(o),`
			`);`
			`endmodule`