mirror of https://github.com/YosysHQ/yosys.git
26 lines
693 B
Verilog
26 lines
693 B
Verilog
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`default_nettype none
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module sync_ram_sdp_dc #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clkw, clkr, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clkw) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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end
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always @(posedge clkr) begin
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp_dc
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