yosys/tests/arch/anlogic/fsm.ys

read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

select -assert-count 6 t:AL_MAP_SEQ

select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/fsm.v`
Cleanup top modules and not used defines 2019-10-04 03:57:47 -05:00			`hierarchy -top fsm`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`proc`
Fixed tests 2019-11-11 08:41:33 -06:00			`flatten`

			`equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic`
			`miter -equiv -make_assert -flatten gold gate miter`
			`sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter`

Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
Cleanup top modules and not used defines 2019-10-04 03:57:47 -05:00			`cd fsm # Constrain all select calls below inside the top module`
Fixed tests 2019-11-11 08:41:33 -06:00
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`select -assert-count 6 t:AL_MAP_SEQ`
Cleanup and formating 2019-10-04 04:09:59 -05:00
Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 13:25:17 -05:00			`select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D`