mirror of https://github.com/YosysHQ/yosys.git
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
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logger -expect log "SAT proof finished - no model found: SUCCESS!" 1
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logger -expect log "Number of cells:.*[\t ]12" 1
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logger -expect log "Number of cells:.*[\t ]20" 1
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logger -expect log "Problem is satisfiable with \\gate.__glift_weight = 11." 1
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logger -expect log "Problem is NOT satisfiable with \\gate.__glift_weight <= 10." 1
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logger -expect log "Wire \\gate.__glift_weight is minimized at 11." 1
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logger -expect log "Specializing .* from file with .* = 1." 2
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logger -expect log "Specializing .* from file with .* = 0." 4
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read_verilog <<EOT
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module mux2(a, b, s, y);
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input a, b, s;
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output y;
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wire s_n = ~s;
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wire t0 = s & a;
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wire t1 = s_n & b;
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assign y = t0 | t1;
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endmodule
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EOT
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techmap
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copy mux2 uut
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copy mux2 spec
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delete mux2
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glift -optimize-precise uut
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glift -create-precise spec
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design -push-copy
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miter -equiv spec uut qbfmiter
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flatten
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delete spec uut
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qbfsat -assume-outputs -assume-negative-polarity -write-solution mux2.soln qbfmiter
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design -pop
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copy uut solved
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qbfsat -specialize-from-file mux2.soln solved
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opt
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miter -equiv spec solved proofmiter
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flatten proofmiter
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sat -prove trigger 0 proofmiter
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delete proofmiter
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stat solved spec
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