mirror of https://github.com/YosysHQ/yosys.git
46 lines
1008 B
Plaintext
46 lines
1008 B
Plaintext
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read_verilog C880.v
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techmap
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flatten
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select C880_lev2
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glift -optimize-precise
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techmap
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opt
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rename C880_lev2 uut
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cd ..
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delete [AIONX][NVXR]2
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read_verilog C880.v
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techmap
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flatten
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select C880_lev2
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glift -create-precise
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techmap
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opt
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rename C880_lev2 spec
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cd ..
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delete [AIONX][NVXR]2
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design -push-copy
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miter -equiv spec uut miter
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flatten
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delete uut spec
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techmap
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opt
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stat miter
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abc -script +print_stats;strash;print_stats;drwsat;print_stats;print_stats;fraig;print_stats;dc2,-l,-b;print_stats;irw,-l,-z;print_stats;refactor,-N,15,-z;print_stats;dch,-S,50000,-C,10000;print_stats;dc2,-l;print_stats;fraig,-C,10000;print_stats miter
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techmap
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opt
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stat
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qbfsat -dump-final-smt2 /tmp/test.smt2 -write-solution C880.soln -show-smtbmc -solver yices -timeout 3600 -nocleanup -assume-outputs -assume-negative-polarity -specialize miter
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design -pop
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stat
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copy uut solved
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qbfsat -specialize-from-file C880.soln solved
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opt solved
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miter -equiv spec solved satmiter
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flatten
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sat -prove trigger 0 satmiter
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delete satmiter
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stat
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shell
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