mirror of https://github.com/YosysHQ/yosys.git
79 lines
3.3 KiB
Coq
79 lines
3.3 KiB
Coq
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// FF mapping
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`ifndef _NO_FFS
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module \$_DFF_N_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
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endmodule
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module \$_DFF_P_ (input D, C, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
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endmodule
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module \$_DFFE_NP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
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endmodule
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module \$_DFFE_PP_ (input D, C, E, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
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endmodule
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module \$_DFF_NN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
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endmodule
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module \$_DFF_NP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
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endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
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endmodule
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
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endmodule
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module \$_DFF_NN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
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endmodule
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module \$_DFF_NP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
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endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
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endmodule
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module \$_DFF_PP1_ (input D, C, R, output Q);
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
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endmodule
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`endif
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