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30 lines
840 B
ReStructuredText
30 lines
840 B
ReStructuredText
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Word-level cells
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----------------
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Most of the RTL cells closely resemble the operators available in HDLs such as
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Verilog or VHDL. Therefore Verilog operators are used in the following sections
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to define the behaviour of the RTL cells.
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Note that all RTL cells have parameters indicating the size of inputs and
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outputs. When passes modify RTL cells they must always keep the values of these
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parameters in sync with the size of the signals connected to the inputs and
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outputs.
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Simulation models for the RTL cells can be found in the file
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:file:`techlibs/common/simlib.v` in the Yosys source tree.
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.. toctree::
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:maxdepth: 2
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/cell/word_unary
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/cell/word_binary
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/cell/word_mux
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/cell/word_reg
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/cell/word_mem
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/cell/word_fsm
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/cell/word_arith
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/cell/word_spec
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/cell/word_formal
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/cell/word_debug
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/cell/word_wire
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