mirror of https://github.com/YosysHQ/yosys.git
12 lines
211 B
Verilog
12 lines
211 B
Verilog
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// Like pack1.v, but results in a simpler network.
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module top(...);
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input a,b,c,d,e,f,g,h;
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wire x = c|d;
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wire y = e&f;
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wire u = a&b;
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wire v = x|y;
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wire w = g&h;
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output s = u|v;
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output t = v|w;
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endmodule
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