2016-03-19 05:09:10 -05:00
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#!/bin/bash
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set -e
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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if [ -z "$1" ]
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then
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libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
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else
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libdir=$1
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fi
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2016-03-19 05:09:10 -05:00
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function xtract_cell_decl()
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{
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for dir in $libdir/xeclib $libdir/retarget; do
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[ -f $dir/$1.v ] || continue
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2019-03-22 08:57:17 -05:00
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[ -z "$2" ] || echo $2
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2018-10-04 04:30:55 -05:00
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egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
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2016-03-19 05:09:10 -05:00
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sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
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s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
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s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
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s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;'
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echo; return
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done
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echo "Can't find $1."
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exit 1
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}
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{
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echo "// Created by cells_xtra.sh from Xilinx models"
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echo
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# Design elements types listed in Xilinx UG953
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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xtract_cell_decl BSCANE2 "(* keep *)"
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# xtract_cell_decl BUFG "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFGCE "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFGCE_1 "(* clkbuf_driver = \"O\" *)"
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#xtract_cell_decl BUFGCTRL "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFGMUX "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFGMUX_1 "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFGMUX_CTRL "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFH "(* clkbuf_driver = \"O\" *)"
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#xtract_cell_decl BUFHCE "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFIO "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFMR "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFMRCE "(* clkbuf_driver = \"O\" *)"
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xtract_cell_decl BUFR "(* clkbuf_driver = \"O\" *)"
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2019-03-22 08:57:17 -05:00
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xtract_cell_decl CAPTUREE2 "(* keep *)"
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2016-03-19 05:09:10 -05:00
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# xtract_cell_decl CARRY4
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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xtract_cell_decl CFGLUT5 "(* clkbuf_sink = \"CLK\" *)"
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2019-03-22 08:57:17 -05:00
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xtract_cell_decl DCIRESET "(* keep *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl DNA_PORT
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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xtract_cell_decl DSP48E1 "(* clkbuf_sink = \"CLK\" *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl EFUSE_USR
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# xtract_cell_decl FDCE
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# xtract_cell_decl FDPE
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# xtract_cell_decl FDRE
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# xtract_cell_decl FDSE
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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xtract_cell_decl FIFO18E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
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xtract_cell_decl FIFO36E1 "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl FRAME_ECCE2
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xtract_cell_decl GTHE2_CHANNEL
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xtract_cell_decl GTHE2_COMMON
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xtract_cell_decl GTPE2_CHANNEL
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xtract_cell_decl GTPE2_COMMON
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xtract_cell_decl GTXE2_CHANNEL
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xtract_cell_decl GTXE2_COMMON
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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# xtract_cell_decl IBUF "(* iopad_external_pin = \"I\" *)"
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xtract_cell_decl IBUF_IBUFDISABLE "(* iopad_external_pin = \"I\" *)"
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xtract_cell_decl IBUF_INTERMDISABLE "(* iopad_external_pin = \"I\" *)"
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xtract_cell_decl IBUFDS "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_GTE2 "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_IBUFDISABLE "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFDS_INTERMDISABLE "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFG "(* iopad_external_pin = \"I\" *)"
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xtract_cell_decl IBUFGDS "(* iopad_external_pin = \"I,IB\" *)"
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xtract_cell_decl IBUFGDS_DIFF_OUT "(* iopad_external_pin = \"I,IB\" *)"
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2019-03-22 08:57:17 -05:00
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xtract_cell_decl ICAPE2 "(* keep *)"
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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xtract_cell_decl IDDR "(* clkbuf_sink = \"C\" *)"
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xtract_cell_decl IDDR_2CLK "(* clkbuf_sink = \"C,CB\" *)"
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xtract_cell_decl IDELAYCTRL "(* keep *) (* clkbuf_sink = \"REFCLK\" *)"
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xtract_cell_decl IDELAYE2 "(* clkbuf_sink = \"C\" *)"
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xtract_cell_decl IN_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
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xtract_cell_decl IOBUF "(* iopad_external_pin = \"IO\" *)"
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xtract_cell_decl IOBUF_DCIEN "(* iopad_external_pin = \"IO\" *)"
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xtract_cell_decl IOBUF_INTERMDISABLE "(* iopad_external_pin = \"IO\" *)"
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xtract_cell_decl IOBUFDS "(* iopad_external_pin = \"IO\" *)"
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xtract_cell_decl IOBUFDS_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
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xtract_cell_decl IOBUFDS_DIFF_OUT "(* iopad_external_pin = \"IO,IOB\" *)"
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xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN "(* iopad_external_pin = \"IO,IOB\" *)"
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xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE "(* iopad_external_pin = \"IO,IOB\" *)"
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xtract_cell_decl ISERDESE2 "(* clkbuf_sink = \"CLK,CLKB,CLKDIV,CLKDIVP,OCLK,OCLKB\" *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl KEEPER
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xtract_cell_decl LDCE
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xtract_cell_decl LDPE
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# xtract_cell_decl LUT1
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# xtract_cell_decl LUT2
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# xtract_cell_decl LUT3
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# xtract_cell_decl LUT4
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# xtract_cell_decl LUT5
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# xtract_cell_decl LUT6
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2019-04-12 11:30:49 -05:00
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#xtract_cell_decl LUT6_2
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl MMCME2_ADV
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xtract_cell_decl MMCME2_BASE
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# xtract_cell_decl MUXF7
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# xtract_cell_decl MUXF8
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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# xtract_cell_decl OBUF "(* iopad_external_pin = \"O\" *)"
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xtract_cell_decl OBUFDS "(* iopad_external_pin = \"O,OB\" *)"
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xtract_cell_decl OBUFT "(* iopad_external_pin = \"O\" *)"
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xtract_cell_decl OBUFTDS "(* iopad_external_pin = \"O,OB\" *)"
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xtract_cell_decl ODDR "(* clkbuf_sink = \"C\" *)"
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xtract_cell_decl ODELAYE2 "(* clkbuf_sink = \"C\" *)"
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xtract_cell_decl OSERDESE2 "(* clkbuf_sink = \"CLK,CLKDIV\" *)"
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xtract_cell_decl OUT_FIFO "(* clkbuf_sink = \"RDCLK,WRCLK\" *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl PHASER_IN
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xtract_cell_decl PHASER_IN_PHY
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xtract_cell_decl PHASER_OUT
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xtract_cell_decl PHASER_OUT_PHY
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xtract_cell_decl PHASER_REF
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xtract_cell_decl PHY_CONTROL
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xtract_cell_decl PLLE2_ADV
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xtract_cell_decl PLLE2_BASE
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2019-03-22 08:57:17 -05:00
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xtract_cell_decl PS7 "(* keep *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl PULLDOWN
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xtract_cell_decl PULLUP
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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#xtract_cell_decl RAM128X1D "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM128X1S "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM256X1S "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM32M "(* clkbuf_sink = \"WCLK\" *)"
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#xtract_cell_decl RAM32X1D "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM32X1S "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM32X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM32X2S "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM64M "(* clkbuf_sink = \"WCLK\" *)"
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#xtract_cell_decl RAM64X1D "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM64X1S "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM64X1S_1 "(* clkbuf_sink = \"WCLK\" *)"
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xtract_cell_decl RAM64X2S "(* clkbuf_sink = \"WCLK\" *)"
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# xtract_cell_decl RAMB18E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
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# xtract_cell_decl RAMB36E1 "(* clkbuf_sink = \"CLKARDCLK,CLKBWRCLK\" *)"
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2016-03-19 05:09:10 -05:00
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xtract_cell_decl ROM128X1
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xtract_cell_decl ROM256X1
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xtract_cell_decl ROM32X1
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xtract_cell_decl ROM64X1
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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#xtract_cell_decl SRL16E "(* clkbuf_sink = \"CLK\" *)"
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#xtract_cell_decl SRLC32E "(* clkbuf_sink = \"CLK\" *)"
|
2019-03-22 08:57:17 -05:00
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xtract_cell_decl STARTUPE2 "(* keep *)"
|
2016-03-19 05:09:10 -05:00
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xtract_cell_decl USR_ACCESSE2
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xtract_cell_decl XADC
|
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} > cells_xtra.new
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mv cells_xtra.new cells_xtra.v
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exit 0
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