yosys/tests/ice40/dffs.v

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module top
    ( input d, clk, output reg q );
	always @( posedge clk )
            q <= d;
endmodule
Fix all comments from PR 2019-08-21 13:52:07 -05:00			`module top`
			`( input d, clk, output reg q );`
Add new tests for ice40 architecture 2019-08-19 23:50:05 -05:00			`always @( posedge clk )`
			`q <= d;`
			`endmodule`