mirror of https://github.com/YosysHQ/yosys.git
58 lines
906 B
Verilog
58 lines
906 B
Verilog
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`timescale 1ns/10ps
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module svinterface1_tb;
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logic clk;
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logic rst;
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logic [21:0] outOther;
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logic [1:0] sig;
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logic [1:0] sig_out;
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logic flip;
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logic [15:0] passThrough;
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integer outfile;
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TopModule u_dut (
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.clk(clk),
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.rst(rst),
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.outOther(outOther),
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.sig(sig),
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.flip(flip),
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.passThrough(passThrough),
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.sig_out(sig_out)
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);
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initial begin
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clk = 0;
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while(1) begin
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clk = ~clk;
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#50;
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end
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end
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initial begin
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outfile = $fopen("output.txt");
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rst = 1;
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sig = 0;
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flip = 0;
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@(posedge clk);
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#(2);
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rst = 0;
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@(posedge clk);
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for(int j=0;j<2;j++) begin
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for(int i=0;i<20;i++) begin
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#(2);
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flip = j;
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sig = i;
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@(posedge clk);
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end
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end
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$finish;
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end
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always @(negedge clk) begin
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$fdisplay(outfile, "%d %d %d", outOther, sig_out, passThrough);
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end
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endmodule
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