mirror of https://github.com/YosysHQ/yosys.git
15 lines
237 B
Plaintext
15 lines
237 B
Plaintext
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read_verilog splice.v
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hierarchy -check; opt
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copy test gold
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cd test
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splice
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# show
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cd ..
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rename test gate
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miter -equiv -make_assert -make_outputs gold gate miter
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flatten miter
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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