mirror of https://github.com/YosysHQ/yosys.git
83 lines
1.2 KiB
Coq
83 lines
1.2 KiB
Coq
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`define MAXQ 2
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module uut (
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input clk,
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input d, r, e,
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output [`MAXQ:0] q
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);
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reg q0;
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always @(posedge clk) begin
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if (r)
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q0 <= 0;
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else if (e)
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q0 <= d;
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end
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reg q1;
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always @(posedge clk, posedge r) begin
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if (r)
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q1 <= 0;
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else if (e)
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q1 <= d;
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end
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reg q2;
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always @(posedge clk, negedge r) begin
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if (!r)
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q2 <= 0;
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else if (!e)
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q2 <= d;
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end
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assign q = {q2, q1, q0};
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endmodule
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`ifdef TESTBENCH
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module testbench;
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reg clk;
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always #5 clk = (clk === 1'b0);
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reg d, r, e;
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wire [`MAXQ:0] q_uut;
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uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut));
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wire [`MAXQ:0] q_syn;
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syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn));
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task printq;
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reg [5*8-1:0] msg;
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begin
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msg = "OK";
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if (q_uut != q_syn) msg = "SYN";
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$display("%6t %b %b %s", $time, q_uut, q_syn, msg);
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if (msg != "OK") $stop;
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end
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endtask
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initial if(0) begin
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$dumpfile("async.vcd");
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$dumpvars(0, testbench);
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end
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initial begin
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@(posedge clk);
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d <= 0;
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r <= 0;
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e <= 0;
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@(posedge clk);
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e <= 1;
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@(posedge clk);
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e <= 0;
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repeat (10000) begin
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@(posedge clk);
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printq;
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d <= $random;
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r <= $random;
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e <= $random;
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end
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$display("OK");
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$finish;
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end
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endmodule
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`endif
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